Link 16 is a widespread tactical wireless networking protocol that is used by front line land, air, and naval systems in the United States, NATO, and allied nations to allow multiple users to share situational awareness data. The protocol is based on an omnidirectional waveform that transmits information in pulses spaced 13 microseconds apart and distributed across 51 frequencies. The data is modulated on each pulse using Continuous Phase Shift Modulation (“CPSM”) which is also a form of Minimum Shift Keying (“MSK”). Each pulse contains 32 symbols or “chips” of information, with each “chip” being 200 nanoseconds in length. According to the TDMA protocol, information is transmitted on a Link 16 network in timeslots that repeat every TDMA frame, or “epoch.”
Messages transmitted on Link 16 networks are grouped in functional areas, and allocated to “Network Participation Groups” (NPGs), also sometimes referred to simply as Participation Groups (PGs). The use of NPGs allows the Link16 network to determine the amount of bandwidth to be allocated for each functional group for the network.
A typical link 16 network is shown in FIG. 1. The blocks 10 in the ring 12 are time slots. Each participant 14 is provided transmit, receive, and relay time slot assignments by a network planner (not shown) prior to start of a mission. The column 16 to the right of the ring 12 illustrates the ability for Link 16 to operate on multiple nets (shown as stacked rings in the column 16). Each of the rings 12 in the column 16 can be replaced, allowing users to form sub-networks or sub-nets allowing them to exchange data using different CDMA and FDMA codes to expand the capability of the network. Details of the construction of these messages can be found in MIL-STD-6016, incorporated herein by reference in its entirety for all purposes.
In order for a Link 16 node to receive a message, it must detect a valid message preamble, which is the first 32 pulses of every Link 16 message. These first 32 pulses that comprise each message preamble are also referred to herein as “sync” pulses. A Link 16 preamble is transmitted on eight frequencies that are known to the receiver, with each frequency being used 4 times in a fixed order. The 32 chips of each preamble pulse are also known to the receiver. So as to determine if a valid message preamble has been received, a digital correlator is used to compare the known bits of each sync pulse with a demodulated bit stream of information from the receiver. The correlator outputs for each sync pulse are summed in a “Delay and Add Pipeline,” and the sum is compared to a minimum detection threshold.
Once a valid preamble has been detected, the Link 16 receiver begins the process of data reception and correlation. The Link 16 digital signal processing is typically performed in a FPGA (Field Programmable Gate Array) device. It will be understood, however, that references to FPGA devices and resources made herein are intended to refer to any electronic resources that are used to implement Link 16 communications.
In addition to issues of background noise and signal strength, successful exchanges of messages over a Link 16 network can be further impeded by self-interference within the network due to multiple users transmitting in the same time slot, as well as by malicious interference jamming directed at the network by a hostile entity.
Various digital signal processing techniques have been proposed to improve the performance of Link 16 by removing interference from the received signal before the correlation process. Due to the complexity of these interference mitigation techniques, and the resulting high demands on FPGA resources, the number of frequencies that can be simultaneously protected by these interference mitigation techniques is typically limited. This limits their effectiveness when applied to the preamble detection process. For example, in the Link 16 receiver of FIG. 2A, four input bit streams F1-F4 are demodulated by four down converters 200 and then analyzed by four correlators 202, but interference mitigation 204 is applied only to the first frequency channel, F1. The correlator outputs are then summed by a summer 206 and the resulting score 214 is compared with a minimum detection threshold.
In addition to the added demand for electronic resources, a common problem with these interference mitigation techniques is that under certain conditions they can actually degrade the performance of the detection process, especially when no actual interference is present.
One approach to solving this problem is to implement an interference recognizer to decide when to turn the mitigation technique on or off. However, such interference recognizers tend to require excessive additional FPGA resources, and do not always reliably detect the presence of interference.
What is needed, therefore, is a method for implementing interference mitigation in a Link 16 receiver that will not require excessive additional electronic resources, and will not degrade performance of the receiver when no interference is present.